As component densities in semiconductor devices increase, use of thin-film transistors also increases. Thin-film transistors typically have poor transistor characteristics. One of these characteristics is the leakage current of the device when it is off, which is call "off current." Theoretically, the off current should be zero when the transistor is off. In reality, the off current for a thin-film transistor typically is unacceptably high. The problem is magnified when there are numerous thin-film transistors in a device, such as a static-random-access memory (SRAM). In an SRAM cell, the load transistors may be thin-film p-channel transistors.
To reduce off current in thin-film p-channel transistors, an offset drain region is used. The offset drain region is that portion of the channel region adjacent to the drain but is not directly above or directly below the gate electrode for that transistor. In many transistors with offset drain regions, the offset drain region is nothing more than an extension of the channel region. As used in this specification, the length of a channel region, offset drain region, main channel section of a channel region, and offset channel section of a channel region is the general direction in which current (whether electrons or holes) primarily flows. An offset drain region typically has a length that generally extends in about the same direction as the length of the channel region. Offset drain regions typically use more substrate area than transistors not having an offset drain region. Also, the offset drain regions may complicate interconnect process sequences particularly in SRAMs. Thin-film transistors in SRAMs are typically formed relatively late in the process. If the transistors occupy a large amount of area, bit line, word line, or V.sub.SS contacts may be difficult to form.